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Integrated Device Technology, Inc.
FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT IDT54/74FCT533T/AT/CT IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FEATURES:
* Common features: - Low input and output leakage 1A (max.) - CMOS power levels - True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) - Meets or exceeds JEDEC standard 18 specifications - Product available in Radiation Tolerant and Radiation Enhanced versions - Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) - Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages * Features for FCT373T/FCT533T/FCT573T: - Std., A, C and D speed grades - High drive outputs (-15mA IOH, 48mA IOL) - Power off disable outputs permit "live insertion" * Features for FCT2373T/FCT2573T: - Std., A and C speed grades - Resistor output (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.)
- Reduced system switching noise
DESCRIPTION:
The FCT373T/FCT2373T, FCT533T and FCT573T/ FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high- impedance state. The FCT2373T and FCT2573T have balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall timesreducing the need for external series terminating resistors. The FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
2564 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T
D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
2564 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-4216/6
6.12
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373/2373T
OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
2564 cnv* 03
32 D1 O1 O2 D2 D3 4 5 6 7 8
1
20 19 18 17 16 15 14
VCC O7
OE
O0
INDEX
D0
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
O3 GND
LE
O4
D4
2564 cnv* 04
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT573/2573T
OE VCC
1
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
2564 cnv* 05
D1
32 D2 D3 D4 D5 D6 4 5 6 7 8
20 19 18 17 16 15 14
O0
D0
INDEX
O1 O2 O3 O4 O5
L20-2
9 10 11 12 13
D7 GND
LE
O7
O6
2564 cnv* 06
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT533
OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 & E20-1 20 19 18 17 16 15 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
2564 cnv* 07
32 D1 O1 O2 D2 D3 4 5 6 7 8
1
20 19 18 17 16 15 14
VCC O7
OE
D0
O0
INDEX
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
LE O3 GND O4 D4
2564 cnv* 08
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (533)(1)
DN H L X Inputs LE H H X Outputs
FUNCTION TABLE (373 and 573)(1)
OE
L L H
ON
L H Z
2564 tbl 01
DN H L X
Inputs LE H H X
OE
L L H
Outputs ON H L Z
2564 tbl 02
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
DEFINITION OF FUNCTIONAL TERMS
Pin Names DN LE Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Complementary 3-State Outputs
2564 tbll 03
OE
ON
ON
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage -0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage -0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current -60 to +120 Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2564 lnk 05
-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 0.5 -60 to +120
V
C C C
W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2564 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current (4) High Impedance Output Current (3-State Output pins) (4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Min., IIN = -18mA
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V VCC = Max., VI = VCC (Max.)
Min. 2.0 -- -- -- -- -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01
Max. -- 0.8 1 1 1 1 1 -1.2 -- 1
Unit V V A A A V mV mA
2564 lnk 06
VCC = Max., VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = -6mA MIL. VIN = VIH or VIL IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L. VCC = Min. IOL = 32mA MIL. VIN = VIH or VIL IOL = 48mA COM'L. VCC = Max., VO = GND (3) VCC = 0V, VIN or VO 4.5V Min. 2.4 2.0 -- -60 -- Typ.(2) 3.3 3.0 0.3 -120 -- Max. -- -- 0.5 -225 Unit V V V mA
VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
1
A
2564 lnk 07
OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -12mA MIL. IOH = -15mA COM'L. IOL = 12mA Min. 16 -16 2.4 -- Typ.(2) 48 -48 3.3 0.3 Max. -- -- -- 0.50 Unit mA mA V V
2564 lnk 08
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling Min. -- -- -- Typ.(2) 0.5 0.15 0.06 Max. 2.0 0.25 0.12 Unit mA mA/ MHz
VIN = VCC FCTxxxT VIN = GND FCT2xxxT
IC
Total Power Supply Current (6)
VIN = VCC
FCTxxxT
-- -- --
1.5 0.6 1.8 0.9
3.5 2.2 4.5 3.2 6.0 (5) 3.4 (5) 14.0 (5) 11.4 (5)
mA
VIN = GND FCT2xxxT FCTxxxT VIN = 3.4 VIN = GND FCT2xxxT VIN = VCC FCTxxxT
-- -- -- --
3.0 1.2 5.0 3.2
VIN = GND FCT2xxxT FCTxxxT VIN = 3.4 VIN = GND FCT2xxxT
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2564 tbl 09
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT373T/2373T/573T/2573T Com'l. Symbol Parameter Conditions(1)
Min.(2) Max.
FCT373AT/2373AT/573AT/2573AT Com'l. Mil.
Min.(2) Max.
Mil.
Min.(2) Max.
Min.(2)
Max.
Unit
tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW
Propagation Delay DN to ON Propagation Delay LE to ON Output Enable Time Output Disable Time Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH
CL = 50pF RL = 500
1.5 2.0 1.5 1.5 2.0 1.5 6.0
8.0 13.0 12.0 7.5 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
8.5 15.0 13.5 10.0 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 5.0
5.2 8.5 6.5 5.5 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
5.6 9.8 7.5 6.5 -- -- --
ns ns ns ns ns ns ns
2564 tbl 10
FCT373CT/2373CT/573CT/2573CT Com'l. Symbol Parameter Conditions(1)
Min.(2) Max.
FCT373DT/573DT Com'l. Mil.
Min.(2) Max.
Mil.
Min.(2) Max.
Min.(2)
Max.
Unit
tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW
Propagation Delay DN to ON Propagation Delay LE to ON Output Enable Time Output Disable Time Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH (3)
CL = 50pF RL = 500
1.5 2.0 1.5 1.5 2.0 1.5 5.0
FCT533T
4.2 5.5 5.5 5.0 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
5.1 8.0 6.3 5.9 -- -- --
1.5 2.0 1.5 1.5 1.5 1.0 3.0
3.8 4.0 4.8 4.0 -- -- --
-- -- -- -- -- -- --
FCT533CT
-- -- -- -- -- -- --
ns ns ns ns ns ns ns
2564 tbl 11
FCT533AT Mil. Com'l. Mil.
Com'l. Symbol Parameter
Com'l.
Mil.
Conditions (1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW
Propagation Delay DN to ON Propagation Delay LE to ON Output Enable Time Output Disable Time Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH
CL = 50pF RL = 500
1.5 2.0 1.5 1.5 2.0 1.5 6.0
10.0 13.0 11.0 7.0 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
12.0 14.0 12.5 8.5 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 5.0
5.2 8.5 6.5 5.5 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
5.6 9.8 7.5 6.5 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 5.0
4.2 5.5 5.5 5.0 -- -- --
1.5 2.0 1.5 1.5 2.0 1.5 6.0
5.1 8.0 6.3 5.9 -- -- --
ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 6.12
2564 tbl 12
6
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2564 drw 09
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed Open
VOUT
500
2564 lnk 13 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2564 drw 10
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2564 drw 11
tSU
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2564 drw 13
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2564 drw 12
CONTROL INPUT tPLZ
0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
6.12
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IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FCT Temp. Range X Family XXXX Device Type X Package X Process Blank B P D SO L E PY Q 373T 573T 533T 373AT 573AT 533AT 373CT 573CT 533CT 373DT 573DT Blank 2 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Shrink Small Outline Package Quarter-size Small Outline Package Non-Inverting Octal Transparent Latch Non-Inverting Octal Transparent Latch Inverting Octal Transparent Latch
High Drive Balanced Drive -55C to +125C 0C to +70C
2564 drw 14
6.12
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